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Overview of Ternary Logic

Ternary logic uses trits of {0, 1, 2}, adding one more state to the binary {0, 1} bits, resulting in a 37% reduction in circuit complexity compared to binary. By manufacturing semiconductors based on ternary logic, the number and area of transistors required to build circuits are reduced, which in turn lowers power consumption.

While increasing the radix to 4, 5, etc., can further reduce area and power consumption compared to ternary, there are practical limits due to signal noise and malfunction issues that arise in actual semiconductor fabrication. Although advances in semiconductor technology may change this in the future, with current silicon and transistor-based semiconductor systems, ternary logic is the most cost-effective multi-valued logic system.

Ternell’s Ternary Logic

Research on ternary logic-based semiconductors has been ongoing. However, previous ternary logic approaches attempted to create the third state by extending binary techniques, which often increased power consumption and thus offered limited benefits.

Ternell’s ternary logic, on the other hand, defines the third state by developing a technology that controls and recognizes current generated by quantum tunneling phenomena in the off state. This enables low-power ternary semiconductors to be implemented in a hybrid manner on the same area as CMOS using existing mass-production foundry processes, making it an economically viable technology.

Binary-Ternary Hybrid Semiconductor Technology Semiconductor Technology

Ternary logic added to conventional binary within the same area and structure as CMOS

Nature electronics (2019)

Ternary logic added to conventional binary within the same area and structure as CMOS

Ternell’s researchers have developed new device structures and process technologies through in-depth studies in semiconductor device physics and electronics, resulting in a new CMOS structure called T-CMOS capable of ternary operations.

T-CMOS forms a new tunnel junction on the drain (output) side of conventional CMOS using special doping techniques, allowing nMOS and pMOS to generate tunneling currents complementarily.

Ternary logic added to conventional binary within the same area and structure as CMOS

Specifically, as one side’s current increases and the other’s decreases, a region emerges where the two tunneling currents are equal, creating a VDD/2 state via voltage dividing. This adds a VDD/2 (1/2) state to the existing GND (0) and VDD (1) states.

T-CMOS does not require new fabrication plants; it can be implemented using existing foundry lines and technologies for mass-producing binary semiconductors.

Other research groups also study ternary logic, but their approaches often rely on new materials or are limited to circuit-level implementations.
Unlike Ternell’s technology, these methods face challenges in integrating on large-area wafers using existing manufacturing lines or suffer from increased circuit complexity, making commercialization difficult.

Technical Excellence of Ternary-CMOS

As semiconductor processes become more miniaturized, leakage current control becomes a major challenge in device implementation. Ternell’s T-CMOS, however, utilizes the tunneling mechanism to control leakage current and employs it as a means to realize ternary logic.

Due to the operational characteristics of T-CMOS, output voltage variation decreases logarithmically, enabling stable ternary operation. Furthermore, by leveraging the unique physical properties of the tunneling mechanism, T-CMOS achieves superior operational characteristics compared to CMOS even under environmental changes such as voltage or temperature fluctuations.

In principle, because T-CMOS uses tunneling current, it is inherently stable against environmental changes. As device technologies advance into 3D structures like FinFETs or GAA, operational stability improves, and thermal reliability surpasses that of CMOS, enabling semiconductors with lower error rates.

Applications of Ternell’s Ternary Semiconductor Technology

Based on the T-CMOS ternary semiconductor technology, Ternell has developed TritCell™, a fundamental memory unit structure. Building on this, Ternell has developed low-power, high-performance SRAM for AI computing.

Additionally, Ternell is developing CIM (Computing In Memory) memory for neuromorphic semiconductors, CAM (Content Addressable Memory) technology that accesses data by searching its contents rather than memory addresses, and PUF (Physical Unclonable Function) semiconductor IP with excellent physical security.

Ternell continues to develop various logic blocks and memory units based on ternary semiconductor technology and is working on UniBrain™, a high-performance AI SoC IP that integrates these components. With Ternell’s semiconductor technology and IP, customers in various industries will be able to easily develop SoCs for AI computing.

Research Paper Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology We demonstrate ternary CMOS (T-CMOS)-based standard ternary inverter (STI) for compact and power scalable multi-valued logic (MVL) circuits. The distinguished mechanism of VG-independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/micrometer level which enables STI operation with ultra-low static power consumption of 7.7 pW/micrometer. Through the STI performance investigation with various T-CMOS structures by using TCAD simulation, advanced nanoscale bulk tri-gate (TG) ternary FinFET (TFinFET) shows highly noise-immune STI operation with a larger static noise margin (SNM) of 94% to the ideal SNM (230mV) than 86% of bulk planar T-CMOS and 75% of SOI T-CMOS technology.

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Research Paper CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-Valued Logic Circuits We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates.

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Research Paper Demonstration of Standard Ternary Inverter Based on CMOS Technology We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I-V characteristics based on off-state mechanism. Though the controllable ’ and ’ with respective design parameters, STI operation at VDD= 1 V have been investigated with static noise margin (SNM) of 210 mV.

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Research Paper Energy Efficient Ternary Device in 28-nm CMOS Technology with Excellent Short-Channel Effect Immunity and Variation Tolerance Characteristics Since the semiconductor industry has entered the hyper-scaling era, which requires a technology to scale itself appropriately to meet the demands of data-intensive computing, binary Boltzmann transistor is facing the integration density limits. One efficient approach to overcome this challenge is the ternary system, where system complexity can be reduced to 63.1% of binary one [2]. Recently, various research efforts of ternary devices have been proposed [3-5]. However, these studies have not verified its ternary function under wafer-scale measurements yet. We have reported a wafer-level integrated and power-scalable ternary device technology (T-CMOS). In this work, we demonstrate a short-channel effect immune and variation tolerant ternary device using 28-nm CMOS foundry.

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Research Paper Low Power and High Density Ternary-SRAM for Always-on Applications Low power consumption is one of the critical design constraints in always-on sensing applications such as wearable, mobile, and edge devices. To accomplish low power design, ternary devices have been investigated, which can reduce system complexity to 63.1 % from binary one. However, ternary memory has yet to be realized because of the lack of proper ternary device technology which has reproducibility, CMOS-compatibility, or low leakage power since most of the ternary devices are based on a multi-threshold scheme. For the development of power scalable ternary device, our group proposed a novel standard ternary inverter (STI) based on nanoscale CMOS technology. Furthermore, we successfully demonstrated ultra-low-power and highly scalable ternary CMOS (T-CMOS) logic by using commercial 110-nm CMOS technology which has the same layout configuration as binary CMOS. In contrast to other multi-VT approaches, T-CMOS has a single VT scheme and operates at the three states in sub-threshold regime. In this work, we report the first demonstration of commercial foundry- processed ternary SRAM operating at VDD= 0.55 V with superior power saving capability compared to CMOS SRAM at the same process node.

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Research Paper Tunnelling-based ternary metal–oxide–semiconductor technology The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.

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